Title :
Experimental results on the impact of factorization and technology independent mapping options on multilevel synthesis
Author :
Abouzeid, P. ; Besson, T. ; Sakouti, K. ; Saucier, G. ; Gaume, F. ; Roane, R.
Author_Institution :
Inst. Nat. Polytech. Grenoble, France
Abstract :
Permanent research efforts are made on various factorization options (algebraic and boolean techniques, extensive use of don´t care. . .). In parallel, similar efforts have been put on adequate factorization improvements or modifications (controlled collapsings) to prepare critical path optimization. The authors investigate the practical efficiency of all these options and report on experimental results when using the combination of all these options in two well known reference synthesis systems (SIS from Berkeley and ASYL from Grenoble)
Keywords :
Boolean functions; circuit layout CAD; logic CAD; many-valued logics; ASYL; SIS; factorization options; multilevel synthesis; reference synthesis systems; Automatic control; Automatic logic units; Boolean functions; CMOS technology; Circuits; Control system synthesis; Data structures; Delay; Libraries; Wiring;
Conference_Titel :
Euro ASIC '92, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-2845-6
DOI :
10.1109/EUASIC.1992.227991