Title :
Double edge triggered feedback flip-flop in sub 100nm technology
Author :
Rasouli, S.H. ; Amirabadi, A. ; Seyedi, A. ; Afzali-Kusha, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ.
Abstract :
In this paper, a new flip-flop called double-edge triggered feedback flip-flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary internal node transition. The subthreshold current in the flip-flops is very low compared to other structures. Reducing the number of transistor in the stack and increasing the number of charge path leads to higher operational speed compared to others flip-flops. The simulation results show an improvement of 44% in the speed and 45% in the static leakage power
Keywords :
circuit feedback; flip-flops; nanoelectronics; trigger circuits; double edge triggered feedback flip-flop; dynamic power consumption reduction; internal node transition; low subthreshold current; static leakage power; CMOS technology; Circuits; Clocks; Energy consumption; Feedback; Flip-flops; Frequency; Latches; Nanoelectronics; Subthreshold current;
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
DOI :
10.1109/ASPDAC.2006.1594698
