• DocumentCode
    3260942
  • Title

    Multi-clock timed networks

  • Author

    Abdulla, Parosh Aziz ; Deneux, Johann ; Mahata, Pritha

  • Author_Institution
    Uppsala Univ., Sweden
  • fYear
    2004
  • fDate
    13-17 July 2004
  • Firstpage
    345
  • Lastpage
    354
  • Abstract
    We consider verification of safety properties for parameterized systems of timed processes, so called timed networks. A timed network consists of a finite state process, called a controller, and an arbitrary set of identical timed processes. In a previous work, we showed that checking safety properties is decidable in the case where each timed process is equipped with a single real-valued clock. It was left open whether the result could be extended to multi-clock timed networks. We show that the problem becomes undecidable when each timed process has two clocks. On the other hand, we show that the problem is decidable when clocks range over a discrete time domain. This decidability result holds when processes have any finite number of clocks.
  • Keywords
    clocks; decidability; finite state machines; formal verification; discrete time domain; finite state process; multi-clock timed networks; parameterized systems; real-valued clock; safety properties verification; timed processes; Automata; Automatic control; Clocks; Control systems; Counting circuits; Encoding; Process control; Protocols; Safety devices; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Logic in Computer Science, 2004. Proceedings of the 19th Annual IEEE Symposium on
  • ISSN
    1043-6871
  • Print_ISBN
    0-7695-2192-4
  • Type

    conf

  • DOI
    10.1109/LICS.2004.1319629
  • Filename
    1319629