DocumentCode
3260982
Title
A CMOS ASIC to implement the TC sublayer in the physical layer of the ATM network
Author
Bulone, J. ; Nava, M. Diaz
Author_Institution
SGS-Thomson Microelectron., Grenoble, France
fYear
1992
fDate
1-5 Jun 1992
Firstpage
344
Lastpage
347
Abstract
The line terminator (LT) is designed to support the transmission convergence (TC) sublayer in the physical layer of the ATM network. It provides high speed data communication; CCITT bit rates of 622.08 Mbit/s and 155.52 Mbit/s are supported. The LT chip has a standard microprocessor interface for ATM components. The transmit and receive sections of the LT chip are independent and can operate simultaneously
Keywords
B-ISDN; CMOS integrated circuits; application specific integrated circuits; asynchronous transfer mode; 155.52 Mbit/s; 622.08 Mbit/s; ATM network; CCITT bit rates; CMOS ASIC; TC sublayer; high speed data communication; line terminator; microprocessor interface; physical layer; transmission convergence; Application specific integrated circuits; Asynchronous transfer mode; B-ISDN; CMOS process; HDTV; High definition video; Intelligent networks; Microprocessors; Physical layer; Videoconference;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '92, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-2845-6
Type
conf
DOI
10.1109/EUASIC.1992.228005
Filename
228005
Link To Document