• DocumentCode
    3261089
  • Title

    Design and evaluation of a submesh allocation scheme for two-dimensional mesh-connected parallel computers

  • Author

    Chang, J. Morris

  • Author_Institution
    Dept. of Comput. Sci., Illinois Inst. of Technol., Chicago, IL, USA
  • fYear
    1997
  • fDate
    18-20 Dec 1997
  • Firstpage
    303
  • Lastpage
    309
  • Abstract
    This paper presents the design and evaluation of a novel submesh allocation algorithm called the Optimized Buddy System which is derived from conventional binary buddy system. Our scheme is made feasible by using a bit-map to represent the status of the processors. The proposed scheme can be mapped into hardware directly to take the advantage of the speed of a pure combinational-logic implementation. Although the buddy system may allocate a submesh that is much larger than the requested size, the logic that finds a free submesh can be augmented by a “bit-flipper” to relinquish the unused portion at the end of the submesh. This effectively eliminates internal fragmentation. The hardware complexity of proposed scheme (i.e. and-gate tree, or-gate tree and bit-flipper) is O(m×n), where m×n is the total number of the processors. The unique blind spot issue of proposed system is also investigated. Simulation results show that the allocation efficiency of the proposed scheme is similar to the one that uses best-fit approach
  • Keywords
    multiprocessor interconnection networks; parallel architectures; processor scheduling; resource allocation; Optimized Buddy System; VLSI systems; binary buddy system; combinational-logic; computer architecture; hardware complexity; mesh connected systems; mesh-connected parallel computers; processor allocation; submesh allocation; Algorithm design and analysis; Computer science; Concurrent computing; Design engineering; Design optimization; Hardware; Memory management; Resource management; Software algorithms; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97) Proceedings., Third International Symposium on
  • Conference_Location
    Taipei
  • ISSN
    1087-4089
  • Print_ISBN
    0-8186-8259-6
  • Type

    conf

  • DOI
    10.1109/ISPAN.1997.645112
  • Filename
    645112