Single chip implementation of real time RNS IIR digital filters

Author

Cardarilli, G.C. ; Lojacono, R. ; Salerno, M. ; Sargeni, F.

Author_Institution

Dept. of Electron. Eng., Rome Univ., Italy

fYear

1992

fDate

1-5 Jun 1992

Firstpage

314

Lastpage

317

Abstract

VLSI realization of single chip IIR digital filters is described. In order to improve speed performance, the arithmetic operations are implemented in parallel, on the basis of residue number system technique. The main feature of the realization is that the delay time related than 100 nsec, so that filters with more than 10 MHz clock rate cane be obtained. Even though an 8 bit wordlength is used for signals, the overall accuracy of the filter is far better than that of an 8 bit conventional realization, because of the favourable properties of the finite arithmetic which makes most inner operations free of arithmetic errors. The final layout has been realized with 1.5 micron CMOS standard cell technology

Keywords

CMOS integrated circuits; VLSI; cellular arrays; digital arithmetic; digital filters; 1.5 micron; 8 bits; CMOS standard cell technology; VLSI realization; arithmetic errors; arithmetic operations; delay time; finite arithmetic; residue number system; single chip IIR digital filters; speed performance; Arithmetic; CMOS technology; Clocks; Delay; Digital filters; Equations; Finite impulse response filter; Parallel processing; Pipeline processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '92, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-2845-6

Type

conf

DOI

10.1109/EUASIC.1992.228012

Filename

228012