DocumentCode :
3261403
Title :
FSM-based transaction-level functional coverage for interface compliance verification
Author :
Su, Man-Yun ; Shih, Che-Hua ; Huang, Juinn-Dar ; Jou, Jing-Yang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2006
fDate :
24-27 Jan. 2006
Abstract :
Interface compliance verification plays a very important role in modern SoC designs. In order to perform a quantitative analysis of simulation completeness, adequate coverage metrics are mandatory. In this paper, we propose a finite state machine (FSM) based transaction-level functional coverage methodology for interface compliance verification. A language, state-oriented language (SOL), is developed to specify functional transactions mainly at the higher FSM level instead of lower logic or signal level. By utilizing SOL, it is simple and rigorous to specify interesting transactions from the specification FSM of the target interface protocol. Experimental results show that the proposed methodology can effectively improve the verification quality as well as increase the efficiency of regression verification.
Keywords :
computer interfaces; finite state machines; formal verification; regression analysis; system-on-chip; FSM; finite state machines; functional transaction; interface compliance verification; regression verification; state-oriented language; target interface protocol; transaction-level functional coverage; Analytical models; Automata; Design engineering; Design methodology; Hardware design languages; Intellectual property; Logic; Performance analysis; Protocols; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Print_ISBN :
0-7803-9451-8
Type :
conf
DOI :
10.1109/ASPDAC.2006.1594726
Filename :
1594726
Link To Document :
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