Sizing CMOS circuits for increased transient error tolerance

The continuous shrinking of microelectronic device sizes with every technology generation, along with the reduction in supply voltages, is causing a significant decrease in circuit noise margins. This leads to increased susceptibility of circuits to transient errors. In this paper, we propose a methodology to increase the robustness of combinational circuits to transient errors by sizing the gates of the circuit in such a way that the number of errors propagated to the primary output is minimized while the timing requirement is met. Using SPICE simulation, we validate that combinational circuits propagate fewer numbers of transient errors to the circuit output after application of our sizing algorithm.