DocumentCode
3261475
Title
Floorplanning with power routing
Author
Brasen, Daniel R.
Author_Institution
Compass Design Automation, San Jose, CA, USA
fYear
1992
fDate
1-5 Jun 1992
Firstpage
165
Lastpage
168
Abstract
Considering power routing during the generation of an initial floorplan minimizes the number of design iterations. However, past power routers only route after hierarchical blocks are synthesized. Floorplanning with power routing involves generating and maintaining symbolic routing before block sizes and pin locations are known. Results considering floorplan level power routing show upto an 11% improvement in chip area
Keywords
VLSI; circuit layout CAD; integrated circuit technology; network routing; power routing; symbolic routing; Design automation; Electric resistance; Electromigration; Power generation; Routing; Signal synthesis; Technology planning; Testing; Topology; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '92, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-2845-6
Type
conf
DOI
10.1109/EUASIC.1992.228030
Filename
228030
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