Title :
Floorplanning with power routing
Author :
Brasen, Daniel R.
Author_Institution :
Compass Design Automation, San Jose, CA, USA
Abstract :
Considering power routing during the generation of an initial floorplan minimizes the number of design iterations. However, past power routers only route after hierarchical blocks are synthesized. Floorplanning with power routing involves generating and maintaining symbolic routing before block sizes and pin locations are known. Results considering floorplan level power routing show upto an 11% improvement in chip area
Keywords :
VLSI; circuit layout CAD; integrated circuit technology; network routing; power routing; symbolic routing; Design automation; Electric resistance; Electromigration; Power generation; Routing; Signal synthesis; Technology planning; Testing; Topology; Wire;
Conference_Titel :
Euro ASIC '92, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-2845-6
DOI :
10.1109/EUASIC.1992.228030
