Optimal TDMA time slot and cycle length allocation for hard real-time systems

Author

Wandeler, Ernesto ; Thiele, Lothar

Author_Institution

Comput. Eng. & Networks Lab., Swiss Fed. Inst. of Technol.

fYear

2006

fDate

24-27 Jan. 2006

Abstract

We present an analytic method to determine the provably smallest possible slot length that must be allocated in a TDMA resource, to serve an event-triggered hard real-time load with arbitrary deterministic timing behavior. Based on this method, we then present constructive methods to find all feasible as well as the optimal cycle length in a TDMA resource, and we show how to determine the minimum required bandwidth of a TDMA resource. We demonstrate the applicability and computational efficiency of the presented methods in a case study of a large distributed embedded system with a TDMA bus, where we find the optimal parameter set for the TDMA bus

Keywords

embedded systems; resource allocation; time division multiple access; timing; arbitrary deterministic timing; computational efficiency; cycle length allocation; embedded systems; hard real-time system; optimal TDMA time slot; Access protocols; Bandwidth; Embedded system; Error correction; Optimal scheduling; Processor scheduling; Real time systems; Resource management; Time division multiple access; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 2006. Asia and South Pacific Conference on

Conference_Location

Yokohama

Print_ISBN

0-7803-9451-8

Type

conf

DOI

10.1109/ASPDAC.2006.1594731

Filename

1594731