DocumentCode
3261492
Title
Post-placement buffer reoptimization
Author
Brasen, D. ; Schaefer, T. ; Ginetti, A. ; Chu, S.
Author_Institution
Compass Design Automation, San Jose, CA, USA
fYear
1992
fDate
1-5 Jun 1992
Firstpage
156
Lastpage
161
Abstract
In this paper the timing of an existing placement is improved by netlist modification. Placement timing is defined as the maximum delay along the most critical path plus the maximum clock skew. Post-placement buffer reoptimization balances clock buffer trees to minimize clock skew and speeds up critical path delays to minimize chip timing. Initial results show upto a 55% reduction in critical path timing with only a 5% increase in area
Keywords
buffer circuits; circuit layout CAD; delays; logic CAD; optimisation; CAD; clock buffer trees; clock skew; critical path timing; maximum delay; netlist modification; post placement buffer-reoptimisation; Capacitance; Circuit synthesis; Clocks; Delay; Design automation; Integrated circuit interconnections; Logic circuits; Logic design; Logic functions; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '92, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-2845-6
Type
conf
DOI
10.1109/EUASIC.1992.228031
Filename
228031
Link To Document