A hierarchical self test scheme for SoCs

Author

Kretzschmar, Claudia ; Galke, Christian ; Vierhaus, Heinrich T.

Author_Institution

Comput. Eng. Group, Brandenburg Univ. of Technol., Cottbus, Germany

fYear

2004

fDate

12-14 July 2004

Firstpage

37

Lastpage

42

Abstract

Complex systems on a chip (SoCs) suffer from a couple of test related problems. In almost any case they contain processor devices and complex on-chip networks that need to be tested under heavily restricted access from the outside. Today multi-processor SoCs (MP-SoCs) are becoming the rule rather than the exception and many SoCs consist of heterogeneous multi-processor networks that are partly asynchronous. Therefore, testing processor structures (logic, busses, memory) is an essential part of the problem. For SoCs in safety-critical applications, self-test functions that work independently from external tester devices are becoming a must. This paper presents a new concept for a tester-independent "bottom up" self-test strategy for multi-processor SoCs.

Keywords

asynchronous circuits; built-in self test; logic design; logic testing; multiprocessing systems; multiprocessor interconnection networks; system buses; system-on-chip; SoC hierarchical self test scheme; bottom up self-test strategy; busses; heterogeneous multiprocessor networks; multiprocessor SoC; on-chip networks; partly asynchronous networks; processor memory; restricted test access; safety-critical applications; tester-independent self-test strategy; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Integrated circuit interconnections; Integrated circuit testing; Logic devices; Logic testing; Production; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International

Print_ISBN

0-7695-2180-0

Type

conf

DOI

10.1109/OLT.2004.1319657

Filename

1319657