• DocumentCode
    3261561
  • Title

    Wire sizing with scattering effect for nanoscale interconnection

  • Author

    Shi, Sean X. ; Pan, David Z.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX
  • fYear
    2006
  • fDate
    24-27 Jan. 2006
  • Abstract
    For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physics-based models, while the scattering impact on nanoscale VLSI interconnect and optimization have not been studied. In this paper, we first present a simple, closed-form scattering effect resistivity model based on extensive empirical studies on measurement data. Then we apply the proposed scattering model to revisit several classic wire sizing/shaping problems. Our experimental results show that if the scattering effect is ignored or characterized inaccurately beyond 65nm, the resulting interconnect optimization might be way off from the real optimal solution, e.g., up to 70% underestimation of the delay, or 20times oversizing. We also obtain the new closed-form wire sizing functions with consideration of scattering effects
  • Keywords
    VLSI; electrical resistivity; integrated circuit interconnections; nanoelectronics; nanowires; scattering; closed-form scattering effect resistivity model; nanoscale interconnection; wire shaping; wire sizing; Capacitance; Carbon nanotubes; Conductivity; Conductors; Copper; Delay effects; Grain boundaries; Particle scattering; Transistors; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 2006. Asia and South Pacific Conference on
  • Conference_Location
    Yokohama
  • Print_ISBN
    0-7803-9451-8
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2006.1594735
  • Filename
    1594735