A 64-bit floating point processing unit for a RISC microprocessor

Author

Kubosawa, Hajime ; Katsuno, Akira ; Takahashi, Hiromasa ; Sato, Tomio ; Suga, Atsuhiro ; Goto, Gensuke

Author_Institution

Fujitsu Laboratories Ltd., Atsugi, Japan

fYear

1992

fDate

1-5 Jun 1992

Firstpage

270

Lastpage

273

Abstract

Describes architecture, layout, and simulation methodology of a high performance 64-bit floating point processing unit (FPU) which is applicable to a RISC microprocessor. The FPU contains a floating point execution unit and a floating point controller for the SPARC S-25 microprocessor. The FPU supports SPARC floating point instructions based on the IEEE Standard for Binary Floating Point Arithmetic (ANSI/IEEE std. 754-1985). Operating frequency is 25 MHz and peak floating point computing performance is 12.5 MFLOPS when it is used with the S-25 SPARC microprocessor. The chip was designed using 0.8 μm CMOS standard cell technology. The chip size is 16.4×16.4 mm and packaged into 179-pin PGA. Total transistor count was approximately 330000

Keywords

CMOS integrated circuits; cellular arrays; microprocessor chips; reduced instruction set computing; satellite computers; 0.8 micron; 16.4 mm; 25 MHz; 64 bit; 64-bit FPU; CMOS; PGA; RISC microprocessor; VLIW; architecture; chip size; coprocessors; floating point controller; floating point execution unit; floating point processing unit; layout; simulation methodology; standard cell technology; transistor count; ANSI standards; CMOS technology; Clocks; Computer architecture; Decoding; Laboratories; Microprocessors; Pipelines; Reduced instruction set computing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '92, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-2845-6

Type

conf

DOI

10.1109/EUASIC.1992.228042

Filename

228042