Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

Author

Bolzani, L. ; Rebaudengo, M. ; Reorda, M. Sonza ; Vargas, F. ; Violante, M.

Author_Institution

Departamento de Engenharia Eletrica, Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil

fYear

2004

fDate

12-14 July 2004

Firstpage

79

Lastpage

84

Abstract

High integration levels, coupled with the increased sensitivity to soft errors even at ground level, make the task of guaranteeing adequate dependability levels more difficult then ever. In this paper, we propose to adopt low-cost infrastructure-intellectual-property (I-IP) cores in conjunction with software-based techniques to perform soft error detection. Experimental results are reported that show the effectiveness of the proposed approach.

Keywords

error detection; fault diagnosis; fault tolerance; fault tolerant computing; industrial property; integrated circuit reliability; redundancy; safety-critical software; system-on-chip; dependability; fault correction; fault detection; fault tolerance; hybrid soft error detection; information redundancy; infrastructure IP cores; low-cost infrastructure-intellectual-property cores; safety-critical applications; Application software; Biomedical computing; Computer aided manufacturing; Computer errors; Costs; Fault tolerance; Fault tolerant systems; Hardware; Redundancy; Software safety;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International

Print_ISBN

0-7695-2180-0

Type

conf

DOI

10.1109/OLT.2004.1319663

Filename

1319663