Title :
A Delay Circuit for Build-Out-Self-Test in 0.18-μm CMOS
Author :
Tianmao, Li ; Toshifumi, Hasimoto ; Yukinori, Kuroki
Author_Institution :
Graduate School of Information Science and Electrical Engineering, Kyushu University, Fukuoka-shi, 819-0382, Japan
Abstract :
This paper describes a digital controlled delay circuit for BOST(build-out-self-test) with picosecond resolution. The proposed circuit operates at 250MHz under 1.8V supply according to Hspice simulation on the extracted layout. The complete design was fabricated in a standard TSMC 0.18μm CMOS process technology. The proposed circuit draws 7mw of static power and occupies an area of 0.09mm2.
Keywords :
Circuit testing; Delay effects; Delay lines; Digital control; Inverters; MOS capacitors; Multiplexing; Phase locked loops; Switches; Voltage-controlled oscillators; CMOS integrated circuit; Coarse; Fine; Phase locked loop; low-voltage design;
Conference_Titel :
Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on
Conference_Location :
Tsinghua University
Print_ISBN :
1-4244-1097-5
Electronic_ISBN :
1-4244-1098-3
DOI :
10.1109/EDST.2007.4289811
