DocumentCode
3261949
Title
Interactive register transfer level synthesis using library blocks
Author
Mignotte, A. ; Bertrand, Marie-Claude ; Crastes, M. ; Fron, Jérôme ; Rampon, Jérôme
Author_Institution
Inst. Nat. Polytech. de Grenoble, France
fYear
1992
fDate
1-5 Jun 1992
Firstpage
53
Lastpage
58
Abstract
The synthesis system presented here starts from an initial register transfer level description. This description uses operators and registers defined in a block library. The system synthesizes automatically a circuit consisting of a datapath and a controller with several data path and controller style possibilities. Optimization of the design reconsidering the separation between the data path and the controller as well as the register allocation is performed in the final step
Keywords
logic CAD; shift registers; specification languages; controller style; datapath; library blocks; register allocation; register transfer level description; Arithmetic; Automatic control; Circuit synthesis; Control system synthesis; Data mining; Design optimization; Flowcharts; Libraries; Registers; Resource management;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '92, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-2845-6
Type
conf
DOI
10.1109/EUASIC.1992.228059
Filename
228059
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