Title :
W/WN/poly gate implementation for sub-130 nm vertical cell DRAM
Author :
Malik, R. ; Clevenger, L. ; McStay, I. ; Gluschenkov, O. ; Robl, W. ; Shafer, P. ; Stojakovic, G. ; Yan, W. ; Naeem, M. ; Ramachandran, R. ; Wong, K. ; Prakash, J. ; Kang, W. ; Li, Y. ; Vollertsen, R. ; Strong, A. ; Bergner, W. ; Divakaruni, R. ; Bronner,
Author_Institution :
Infineon Technol. Corp., Hopewell Junction, NY, USA
Abstract :
In this paper, we present the implementation of W/WN/poly gates in a 135 nm sub-8F2 vertical cell DRAM technology with dual gate oxide planar support transistors. Key features include low sheet resistance wordlines, high performance peripheral logic circuitry and a scalable memory cell array. A process flow detailing the decoupling of the array and support regions of the DRAM to achieve planar support transistors with L/sub eff/(nFET)<140 nm is discussed.
Keywords :
CMOS memory circuits; DRAM chips; dielectric thin films; electric resistance; elemental semiconductors; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; silicon; tungsten; tungsten compounds; 130 nm; 135 nm; 140 nm; DRAM support regions; W-WN-Si; W/WN/poly gate implementation; W/WN/poly gates; array decoupling; dual gate oxide planar support transistors; effective channel length; low sheet resistance wordlines; peripheral logic circuitry; planar support transistors; process flow; scalable memory cell array; vertical cell DRAM; vertical cell DRAM technology; Logic arrays; Logic circuits; Microelectronics; Oxidation; Random access memory; Research and development; Silicon compounds; Sputter etching; Technological innovation; Transistors;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934932
