Title :
Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs
Author :
Nakamura, Y. ; Asano, I. ; Hiratani, M. ; Saito, T. ; Goto, H.
Author_Institution :
Device Dev. Dept., ELPIDA MEMORY Inc., Sagamihara, Japan
Abstract :
We demonstrate that an amorphous TaN layer with no grain boundaries shows a good oxidation-resistant performance after forming and annealing the Ta/sub 2/O/sub 5/ dielectric of MIM capacitors for DRAM applications at 550/spl deg/C in O/sub 2/ ambient. We fabricated an MIM-Ta/sub 2/O/sub 5/ capacitor with a concave-type Ru storage node on the TaN barrier metal. This showed a contact resistivity of 0.27 k/spl Omega//spl middot//spl mu/m/sup 2/, a capacitance of 20 fF/bit, and a leakage current of 0.9 fA/bit (-1 to 1 V). We further fabricated a crown-type Ru electrode to demonstrate scalability to 0.10 /spl mu/m design rules.
Keywords :
DRAM chips; MIM devices; annealing; capacitance; chemical interdiffusion; contact resistance; diffusion barriers; electrical resistivity; electrolytic capacitors; integrated circuit metallisation; leakage currents; oxidation; tantalum compounds; -1 to 1 V; 0.1 micron; 550 C; DRAM applications; DRAMs; MIM capacitors; MIM-Ta/sub 2/O/sub 5/ capacitor; MIM-Ta/sub 2/O/sub 5/ capacitors; O/sub 2/; O/sub 2/ anneal ambient; Ta/sub 2/O/sub 5/ dielectric; Ta/sub 2/O/sub 5/-Ru; TaN; TaN barrier metal; amorphous TaN layer; annealing; capacitance; concave-type Ru storage node; contact resistivity; crown-type Ru electrode; design rules; forming; grain boundaries; leakage current; oxidation-resistant amorphous TaN barrier; oxidation-resistant performance; scalability; Amorphous materials; Annealing; Capacitance; Conductivity; Dielectrics; Electrodes; Grain boundaries; Leakage current; MIM capacitors; Random access memory;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934936
