Title :
FDD based technology mapping for FPGA
Author :
Schubert, E. ; Kebschull, U. ; Rosenstiel, W.
Author_Institution :
Lehrstuhl fur Tech. Informatik, Tubingen Univ., Germany
Abstract :
Functional decision diagrams (FDD) are shown to be a very efficient alternative to binary decision diagrams (BDD). FDDs are a representation in the functional domain, since they are based on the Reed-Muller Expansion and not on the sum-of-products form, which is suited to the operational domain. This paper introduces a technology mapping algorithm based on the FDDs and performing a direct mapping to look-up table FPGA. One can keep the main property of FDDs-their compactness-to obtain good results in very short CPU times
Keywords :
Boolean functions; logic CAD; logic arrays; table lookup; CPU times; FDD based technology mapping; FPGA; Reed-Muller Expansion; compactness; functional decision diagram; functional domain; look-up table; Binary decision diagrams; Boolean functions; Circuits; Field programmable gate arrays; Logic devices; Partitioning algorithms; Programmable logic arrays; Programmable logic devices; Table lookup; Wiring;
Conference_Titel :
Euro ASIC '92, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-2845-6
DOI :
10.1109/EUASIC.1992.228065
