Synthesis on multiplexer-based programmable devices using (ordered) binary decision diagrams

Presents synthesis techniques on the Actel multiplexer-based programmable gate arrays. The internal structure of these devices is exploited through binary decision diagrams based algorithms. According to the speed/area trade-off, either classical or reduced ordered Binary Decision Diagrams are used. Emphasis is put on the determination of a good ordering for the ROBDD construction. Results on a large set of international benchmarks and comparisons with existing work are provided