Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMs

Author

Chu, C.M. ; Kiyotoshi, M. ; Niwa, S. ; Nakahira, J. ; Eguchi, K. ; Yamazaki, S. ; Tsunoda, K. ; Fukuda, M. ; Suzuki, T. ; Nakabayashi, M. ; Tomita, H. ; Shiah, C.M. ; Matsunaga, D. ; Hieda, K.

fYear

2001

fDate

12-14 June 2001

Firstpage

43

Lastpage

44

Abstract

We have developed a cylindrical Ru/ST/Ru capacitor for gigabit-scale DRAMs. Using cylindrical CVD-Ru as a storage node (SN), a new 2-step CVD-ST was employed to improve ST step coverage, surface morphology and to control composition at the Ru/ST interface. A SiO/sub 2/ equivalent thickness (t/sub eq/) of 0.6 nm and cell capacitance of 18 fF/cell with leakage current of 0.1 fA/cell at /spl plusmn/0.7 V applied voltage has been achieved on a 256K cylindrical Ru/ST/Ru capacitor array.

Keywords

DRAM chips; MIM devices; capacitance; chemical vapour deposition; crystal morphology; interface structure; leakage currents; ruthenium; strontium compounds; thin film capacitors; 0.11 micron; 0.7 V; 256 kbit; DRAMs; Ru-SrTiO/sub 3/-Ru; Ru/ST interface; ST step coverage; SiO/sub 2/; SiO/sub 2/ equivalent thickness; applied voltage; cell capacitance; composition control; cylindrical CVD-Ru storage node; cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology; cylindrical Ru/ST/Ru capacitor; cylindrical Ru/ST/Ru capacitor array; leakage current; surface morphology; two-step CVD-ST; Annealing; Capacitance; Crystallization; Engine cylinders; Leakage current; MIM capacitors; Random access memory; Surface morphology; Temperature; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934938

Filename

934938