Statistical corner conditions of interconnect delay (corner LPE specifications)

Timing closure in LSI design becomes more and more difficult. But the conventional interconnect RC extraction method have over-margins caused by its corner conditions settings. In this paper, statistical corner conditions using the independence of variations between process parameters and between interconnect layers are proposed. As a result, the fast-to-slow guardband decreases by half in average, compared to the conventional method. The proposed method is ready for implementation to LPE tools