High performance 40 nm vertical MOSFET within a conventional CMOS process flow

Author

Josse, E. ; Skotnicki, T. ; Jurczak, M. ; Paoli, M. ; Tormen, B. ; Dufartre, D. ; Ribot, P. ; Villaret, A. ; Sondergard, E.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2001

fDate

12-14 June 2001

Firstpage

55

Lastpage

56

Abstract

We present here 40 nm vertical MOSFETs fabricated using the most standard CMOS process flow. At the expense of four additional (but still conventional) steps, both planar and vertical devices can be co-integrated within the same flow. Our process is fully described and the vertical transistors are characterized. Very good device performances are obtained at 1 V supply voltage with relaxed gate oxide thickness. Therefore, our vertical MOSFET may constitute an interesting alternative for high performance planar devices in case aggressive scaling of oxide thickness fails.

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; nanotechnology; semiconductor device manufacture; semiconductor device measurement; 40 nm; CMOS process flow; aggressive oxide thickness scaling; device performances; gate oxide thickness; planar devices; planar/vertical device co-integration; standard CMOS process flow; supply voltage; vertical MOSFET; vertical MOSFET fabrication; vertical transistors; CMOS process; CMOS technology; Capacitance; Chemical technology; Etching; Ion implantation; MOSFET circuits; Microelectronics; Silicon; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934944

Filename

934944