Low resistivity bcc-Ta/TaN/sub x/ metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450/spl deg/C

Author

Shimada, H. ; Ohshima, I. ; Nakao, S.-I. ; Nakagawa, M. ; Kanemoto, K. ; Hirayama, M. ; Sugawa, S. ; Ohmi, T.

Author_Institution

Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan

fYear

2001

fDate

12-14 June 2001

Firstpage

67

Lastpage

68

Abstract

We have developed a low-resistivity metal gate metal-nitride-semiconductor (MNS) FET technology with conventional plane gate structure using fully low-temperature processing. The gate stack consists of directly grown silicon nitride (Si/sub 3/N/sub 4/) dielectric using high-density plasma and bcc-phase tantalum (/spl sim/15 /spl mu//spl Omega/cm)/tantalum nitride (bcc-Ta/TaN/sub x/) stacked metal gate below 1.0 /spl Omega//sq. In order to avoid deterioration of the metal gate system, we adopted low-temperature S/D annealing by the solid phase epitaxy (SPE) method. In this paper, we demonstrate the excellent characteristics of fully-depleted silicon-on-dielectric (FDSOI) metal gate MNSFETs with conventional plane gate structure using fully low-temperature processing below 450/spl deg/C.

Keywords

MISFET; annealing; dielectric thin films; plasma deposition; silicon-on-insulator; solid phase epitaxial growth; tantalum; tantalum compounds; 15 muohmcm; 450 C; FDSOI metal gate MNSFETs; Si-SiO/sub 2/; Ta-TaN-Si/sub 3/N/sub 4/-Si; bcc-Ta/TaN/sub x/ metal gate MNSFETs; bcc-Ta/TaN/sub x/ stacked metal gate; bcc-phase tantalum/tantalum nitride stacked metal gate; directly grown Si/sub 3/N/sub 4/ dielectric; fully-depleted silicon-on-dielectric metal gate MNSFETs; gate stack; high-density plasma growth; low-temperature S/D annealing; low-temperature processing; metal gate metal-nitride-semiconductor FET technology; metal gate system; plane gate structure; resistivity; silicon nitride; solid phase epitaxy; Annealing; Conductivity; Dielectric substrates; Industrial electronics; Leakage current; MOS capacitors; MOSFETs; Plasma devices; Plasma materials processing; Plasma temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934950

Filename

934950