Title :
A Hardware-efficient Architecture For 3-D Graphics Processor
Author :
Liang, Bor-Sung ; Nieh, You-Cheng ; Niou, Yih-Pwu ; Jen, Chein-Wei ; Chuang, Gene
Keywords :
Acceleration; Buffer storage; Costs; Graphics; Hardware; Pipeline processing; Pixel; Registers; Rendering (computer graphics); Testing;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-4131-7
DOI :
10.1109/VTSA.1997.614735
