Title :
Impact of CMOS process scaling and SOI on the soft error rates of logic processes
Author :
Hareland, S. ; Maiz, J. ; Alavi, M. ; Mistry, K. ; Walsta, S. ; Changhong Dai
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Technology scaling, reduction in operating voltages, and the increase in cache size and circuit complexity have been key enablers to achieving the performance improvement expectation dictated by Moore´s Law. The resulting reduction in the node charge of circuit latches and cache cells has resulted in an ever increasing soft error rate (SER) estimation for logic components. This paper reports the SER impact of process scaling over four technology generations (0.35, 0.25, 0.18, 0.13 /spl mu/m) and provides an experimental assessment of alpha and, for the first time, neutron SER on advanced SOI processes, which have been considered as a possible method to reduce the SER of advanced technologies.
Keywords :
CMOS digital integrated circuits; alpha-particle effects; cache storage; circuit complexity; error analysis; error statistics; flip-flops; integrated circuit design; integrated circuit measurement; neutron effects; silicon-on-insulator; 0.13 micron; 0.18 micron; 0.25 micron; 0.35 micron; CMOS process scaling; Moore´s Law; SER; SOI; SOI processes; Si-SiO/sub 2/; alpha SER; cache cells; cache size; circuit complexity; circuit latches; logic components; logic processes; neutron SER; node charge reduction; operating voltage reduction; performance improvement expectation; process scaling; soft error rate estimation; soft error rates; technology generations; technology scaling; CMOS process; CMOS technology; Complexity theory; Error analysis; Estimation error; Latches; Logic circuits; Moore´s Law; Neutrons; Voltage;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934953
