Verification of the VLSI-/370 microprocessor

Author

Gerst, Harald

Author_Institution

IBM Lab., Boeblingen, West Germany

fYear

1989

fDate

8-12 May 1989

Abstract

The author discusses the development of the VLSI-/370 microprocessor, especially the top-down verification process mainly based on the multilevel design verification system presented by W. Roesner (1988). The focus is on the functional design verification, which is based on various simulation processes. A major objective is to start the verification process as early as possible, long before the design is complete. This objective is important also for microcode and testcase development. To achieve this goal, a set of specification languages for different levels of abstraction has been developed in order to generate and simulate models composed even of mixes of these levels

Keywords

VLSI; integrated circuit testing; logic CAD; logic testing; microprocessor chips; VLSI-/370 microprocessor; abstraction; functional design verification; microcode; multilevel design verification system; simulation processes; specification languages; testcase development; top-down verification process; Clocks; Discrete event simulation; Laboratories; Logic design; Microprocessors; Monitoring; Silicon; Testing; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '89., 'VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks', Proceedings.

Conference_Location

Hamburg

Print_ISBN

0-8186-1940-6

Type

conf

DOI

10.1109/CMPEUR.1989.93498

Filename

93498