Energy-delay performance of capacitive threshold logic (CTL) circuits for threshold detection

Digital threshold detection is a fundamental logic function that is heavily utilized in a large family of arithmetic processors and neural networks. While recently proposed capacitive threshold logic (CTL) design technology promises to offer a compact and effective solution to threshold detection, its potential to scale to different problem sizes was not previously quantified as compared to traditional CMOS implementations. In this work, CTL complexity, delay, power, and energy-delay product have been comparatively analyzed against compound, standard gate, and transmission-gate based traditional CMOS implementations of digital threshold detection. It is demonstrated by the results that CTL gains delay advantage over the alternate implementations as the number of inputs increase from few to ~10. However, analog nature of the CTL makes it challenging to scale the threshold detection to many more inputs. In addition, energy dissipated by CTL is likely to fall between that of compound CMOS and design using standard gates.