Title :
Single chip video processor for digital HDTV
Author :
Yamauchi, Hideki ; Okada, Shigeyuki ; Taketa, Kazuo ; Mihara, Yoshikazu ; Harada, Yasoo
Author_Institution :
Sanyo Electr. Co. Ltd., Gifu, Japan
Abstract :
We have developed a new high-performance video system LSI using a 0.25 μm CMOS technology for Japan BS digital broadcasting launched in December 2000. The LSI integrates all the necessary functions for video decoding into a single chip and employs efficient architectures which are parallel processing and have parallel data bus architecture for decoding transport streams efficiently
Keywords :
CMOS digital integrated circuits; decoding; digital signal processing chips; digital video broadcasting; high definition television; integrated circuit layout; large scale integration; parallel architectures; television receivers; video signal processing; 0.25 micron; CMOS technology; Japan BS digital broadcasting; architectures; decoding; digital HDTV; high-performance video system LSI; parallel data bus architecture; parallel processing; single chip video processor; transport streams; video decoding; Bandwidth; Clocks; Computer architecture; Decoding; Digital video broadcasting; HDTV; Hardware; Large scale integration; SDRAM; Streaming media;
Conference_Titel :
Consumer Electronics, 2001. ICCE. International Conference on
Conference_Location :
Los Angeles, CA
Print_ISBN :
0-7803-6622-0
DOI :
10.1109/ICCE.2001.935221
