3264168

A Shallow-´ikench Isolation Study For 0.18pm Cmos Technology With Emphasis On The Effects Of Well Design, Channel-stop Implants, Trenchl Depth, And Salicide Process

Murtaza, Syed Shariyar ; Chatterjee, A. ; Mei, Paul ; Amerasekera, A. ; Nicollian, P. ; Kittl, J. ; Breedijk, T. ; Hanratty, M. ; Nag, S. ; Ali, I. ; Rogers, D. ; Chen, I.C.

1997

3-5 June 1997

133

137

CMOS process; CMOS technology; Capacitance; Chemical processes; Chemical technology; Implants; Instruments; Isolation technology; Measurement; Meeting planning;

English

ieee

VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on

Taipei, Taiwan

1524-766X

0-7803-4131-7

conf

10.1109/VTSA.1997.614744

614744