DocumentCode
3264174
Title
Threshold gate network synthesis
Author
Stabler, E.P.
fYear
1965
fDate
6-8 Oct. 1965
Firstpage
5
Lastpage
11
Abstract
A method of synthesizing networks of threshold gates is described. The method makes use of the solutions to the dual of a set of inequalities to guide the design. The procedure is suitable for a variety of network topologies, for multiple output networks, and for partially specified functions. The procedures described are suited to automatic computation. A program for performing logic design using these procedures has been written and tested.
Keywords
Network synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Switching Circuit Theory and Logical Design, 1965. SWCT 1965. Sixth Annual Symposium on
Conference_Location
Ann Arbor, MI, USA
Type
conf
DOI
10.1109/FOCS.1965.32
Filename
5397264
Link To Document