Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm

Very high spectral efficiency and data rates are among the goals of future wireless communication systems. A strong candidate for meeting the requirements is the use of multiple antennas at both the transmitter and the receiver, known as multiple-input multiple-output (MIMO) communications. Sphere detectors have been proposed to be used in MIMO reception to achieve or approximate the optimal maximum likelihood detection with reduced computational complexity. Furthermore, list sphere detectors (LSDs) can be used to approximate the maximum a posteriori detection in channel coded systems. The K-best LSD is a particularly interesting LSD variant with predetermined computational complexity and fixed throughput. In this paper, an application-specific instruction set processor is designed for the K-best LSD using transport triggered architecture. 2 × 2 64-level quadrature amplitude modulation transmission scheme with 16-bit arithmetic and a list size of 16 is used as a baseline design target. List size and word length simulations are presented to justify the choices. The designed processor has a significant amount of general-purpose properties, and it reaches a detection throughput of 7.6 Mbps with a hardware complexity of only 25 000 gate equivalents.