DocumentCode :
3264442
Title :
An instruction set extension for java bytecodes translation acceleration
Author :
Sideris, Isidoros ; Pekmestzi, Kiamal ; Economakos, George
Author_Institution :
Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens
fYear :
2008
fDate :
21-24 July 2008
Firstpage :
116
Lastpage :
123
Abstract :
Java has become popular in a wide range of applications. Just-in-time translation is crucial for providing efficient execution of Java programs. This paper presents an architecture extension to RISC processors that accelerates Java bytecodes translation. Our results show that the incorporation of this technique in a 4-way superscalar RISC and in one high performance embedded processor gives an average speedup of 2.95x and 2.29x respectively. A first order approximation using ASIC synthesis tools shows that this acceleration is performed with only a small increase in hardware.
Keywords :
Java; application specific integrated circuits; approximation theory; reduced instruction set computing; ASIC synthesis tools; Java bytecodes translation; Java bytecodes translation acceleration; RISC processors; architecture extension; first order approximation; instruction set extension; Acceleration; Application software; Computer aided instruction; Hardware; Java; Optimization methods; Reduced instruction set computing; Registers; Software performance; Virtual machining;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. SAMOS 2008. International Conference on
Conference_Location :
Samos
Print_ISBN :
978-1-4244-1985-2
Type :
conf
DOI :
10.1109/ICSAMOS.2008.4664854
Filename :
4664854
Link To Document :
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