A priority-expression-based burst scheduling of memory reordering access

The performance of modern computer system is greatly limited by the bandwidth of DRAM-based memory. Altering the sequence of main memory accesses can reduce observed access latency, therefore improve bus utilization. While previous reordering mechanisms consider factors related to memory access separately, this paper groups several factors together to build a priority expression for bank arbitration based on burst scheduling. The expression considers three factors: wait time of a burst, burst length, and priority of read or write accesses. To make the expression suitable for both read and write accesses, write queue in a bank is designed to buffer bursts, which are defined to be clusters of row hits, other than single write accesses. Experiment results from a modified M5 simulator running selected SPEC CPU2000 and Stream benchmarks show that the priority-expression-based burst scheduling improves the bus utilization about 74% and reduces the execution time 41% over the conventional in-order memory scheduling. It also outperforms burst scheduling 9% and 5% in bus utilization and execution time reduction respectively. The priority-expression-based burst scheduling is proved to be feasible.