FPGA implementation of fast radix 4 division algorithm

The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefits of custom hardware but without the high cost of custom silicon implementations. In this paper, we present the adaptation of a fast radix 4 division algorithm (Srinivas and Parthi, 1994) for lookup table based FPGAs implementation. In this algorithm, the quotient digits are determined by observing three most-significant radix 2 digits of the partial remainder and independent of the divisor. The implementation has been done with Xilinx technology and FPGA-Advantage CAD tools.