DocumentCode
3265346
Title
Verification strategy determination using dependence analysis of transaction-level models
Author
Regimba, Sébastien ; Savaria, Yvon ; Bois, Guy
Author_Institution
Dept. of Electr. Eng., Ecole Polytechnique de Montreal, Que., Canada
fYear
2004
fDate
19-21 July 2004
Firstpage
87
Lastpage
92
Abstract
It is well known that functional verification is a real bottleneck in any digital design development. A robust verification strategy should specify which testbenches are required to verify a system. With a modular system, the determination of which testbenches are required to confirm successful integration of each module is generally done in an ad-hoc fashion. In this paper, we propose a systematic approach supported by a tool to determine effective module combinations that should be verified when integrating a modular system. A goal of verification being to detect errors, it is valuable to create the most favorable situation to detect them. Our proposed approach is based on a static dependence analysis of a transaction-level model and the evaluation of module combinations using a verifiability metric. Using our methodology, we are able to provide quantitative results in order to help verification engineers determine which module combinations are the most appropriate for integration.
Keywords
formal verification; software engineering; systems analysis; digital design; functional verification; static dependence analysis; transaction-level models; verification strategy determination; Abstracts; Design engineering; Digital systems; Hardware; High level languages; Microelectronics; Robustness; Software engineering; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on
Print_ISBN
0-7695-2182-7
Type
conf
DOI
10.1109/IWSOC.2004.1319856
Filename
1319856
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