A tapered partitioning method for “delay energy product” optimization in global interconnects

The delay of global interconnects increases with technology scaling because their thickness to width aspect ratio tend to increase with scaling, while the lengths remain constant or even increase. The buffer insertion technique is generally used to reduce the delay of long global interconnects. In this paper, a new method for optimization of the global interconnects for high performance VLSI circuits in VDSM technologies is presented. A long global interconnect is divided into unequal segments with unequal buffer sizes between them. Following that a generalized analytical method is proposed to optimize the delay-energy product (FOM). In this work, we use the genetic algorithm (GA) to optimize the delay-energy product. Eventually, we compare our method with the method of equal wire segmentation with equal buffer sizing, which also has been optimized using GA algorithm.