• DocumentCode
    3265655
  • Title

    A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture

  • Author

    Ling-zhi, Liu ; Lin, Qiu ; Meng-tian, Rong ; Li, Jiang

  • Author_Institution
    Dept. of Electron. Eng., Shanghai Jiao Tong Univ., China
  • fYear
    2004
  • fDate
    19-21 July 2004
  • Firstpage
    158
  • Lastpage
    161
  • Abstract
    A design of 2-D forward and inverse integer transform processor is presented, which is suitable for MPEG-4 AVC/H.264 visual profile. The comparability between the forward and inverse transform and the symmetry of their arithmetic has been utilized in architecture. According to this design, 2-D transform is implemented by using duplicated 1-D transform. Parallel register array are used to realize the transpose operation. Under 0.35um technology, the logic gate count is only 3524 when the maximum frequency is more than 120MHz.
  • Keywords
    logic gates; parallel architectures; transforms; video coding; 0.35 micron; 1D transform; 2D forward integer transform processor; 2D transform; MPEG-4 AVC/H.264 visual profile; inverse integer transform processor; logic gate count; parallel architecture; parallel register array; Conferences; Real time systems; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on
  • Print_ISBN
    0-7695-2182-7
  • Type

    conf

  • DOI
    10.1109/IWSOC.2004.1319870
  • Filename
    1319870