Technologies for a mobile multimedia microprocessor

The market for such mobile digital consumer products as cellular phones, digital cameras, PDAs, and CISs (car information systems) has been greatly expanding in recent years. In such equipment, multimedia data, i.e. data that might include video, audio, and graphics components, has to be processed at high speeds and with low levels of power consumption. This also has to be achieved at low cost. In the paper, up-to-date technologies used in the SH-X are introduced. This mobile multimedia microprocessor was recently developed with mobile digital consumer appliances as the major target market. In particular, features of the micro-architecture of the processor core and some newly developed low-power techniques are described. Architectural points to be covered include an efficient pipelining scheme that achieves 720 MIPS at 400 mW or 360 MIPS at 80 mW, DSP/FPU features, and a Java acceleration method that attains 6.55 ECM/MHz. The SoC using the SH-X for 3G cellular phones is introduced and techniques through which standby power consumption is dramatically reduced are explained.