Title :
VLSI implementation of full pixel motion estimation processor for MPEG-4 AS profile
Author :
He, Wei-feng ; Mao, Zhi-gang ; Gao, Zhi-Qiang ; Ye, Yi-Zheng
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., China
Abstract :
Efficient 1D and 2D mixed motion estimation array architectures for MPEG-4 AS profile video encoding are presented in this paper. To reduce the utilization of the global bus to the external memory and to improve the computation efficiency of the array, a novel local memory scheme and an improved 2D systolic array architecture for 16×16 macroblock motion estimation are proposed. For 8×8 block motion estimation, a 1D broadcast array architecture is also presented. The motion estimation processor is implemented using TSMC 0.25 μm 1-poly 5-metal CMOS technology, which occupies a silicon area of 3.19×3.19mm2. Experimental results show that it is able to estimate texture motion vectors of MPEG-4 AS profile in ITU-R601 format (720×576 at 25 Hz/PAL) in real-time at around 93.7 MHz.
Keywords :
CMOS digital integrated circuits; VLSI; image texture; microprocessor chips; motion estimation; systolic arrays; video coding; 0.25 micron; 1D broadcast array architecture; 1D/2D mixed motion estimation; 25 Hz; 2D systolic array architecture; 3.19 mm; 414720 pixel; 576 pixel; 720 pixel; 93.7 MHz; CMOS; ITU-R601 format; MPEG-4 AS profile; VLSI implementation; external memory; full pixel motion estimation processor; global bus; local memory scheme; macroblock motion estimation; texture motion vectors; video encoding; Broadcasting; CMOS process; CMOS technology; Computer architecture; Encoding; MPEG 4 Standard; Motion estimation; Silicon; Systolic arrays; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435143
