Design of three important peripheral circuits of SRAM based on 9T cell

Read stability issue is becoming more and more concerned in accordance with rapid development of CMOS IC fabrication technology. A new nine transistor (9T) SRAM cell with enhanced stability during a read operation and reduced power consumption is proposed recently. To put it into practical an SRAM based on it needs to be built. This paper designs three peripheral circuits that are needed in the building process, including row-selecting circuit suitable for the dual control signal character of 9T SRAM cell, simplified writing circuit that can effectively pull down the bit-lines and choose which to pull with only three N-type transistors and power-reduced sense amplifier with its switch transistor controlled by the logic `and´ result of one external and two internal signals that can shut down the circuit when there is enough voltage difference between outputs. The active power consumption of the sense amplifier with and-gate is 38% lower than the one without it. An 8-kb SRAM based on 9T cell using peripheral circuits proposed in this paper is built, and the correctness of the simulation result of its functionality shows that SRAM based on 9T cell can work well with proposed peripheral circuits.