Reconfigurable 2.5 GHz phase-locked loop for system on chip applications

Author

Iniewski, K. ; Syrzycki, M. ; Magierowski, S.

Author_Institution

Dept. of ECE, Alberta Univ., Edmonton, Alta., Canada

fYear

2004

fDate

19-21 July 2004

Firstpage

314

Lastpage

317

Abstract

2.5 GHz phase-locked loop (PLL) suitable for system-on-the-chip (SOC) implementation is presented. PLL can be configured as a clock multiplication unit (CMU) or as a clock recovery unit (CRU) for data muxing or jitter clean-up applications. It uses a phase-frequency detector (PFD), a low voltage charge-pump, and a low power H-bridge output driver. Phase locked-loop architecture is of Type IV that results in superior performance for power supply rejection ratio (PSRR). The circuit has been implemented in 0.18 μm standard CMOS process, occupies 1230 μm by 248 μm and dissipates 128 mW from a 1.8V power supply.

Keywords

CMOS digital integrated circuits; clocks; detector circuits; jitter; phase locked loops; reconfigurable architectures; system-on-chip; 2.7E09 Hz; H-bridge output driver; charge-pump; clock multiplication unit; clock recovery unit; data muxing; jitter clean-up; phase-frequency detector; phase-locked loop; power supply rejection ratio; reconfigurable architecture; system-on-chip applications; Charge pumps; Clocks; Driver circuits; Jitter; Low voltage; Phase detection; Phase frequency detector; Phase locked loops; Power supplies; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on

Print_ISBN

0-7695-2182-7

Type

conf

DOI

10.1109/IWSOC.2004.1319900

Filename

1319900