Timing specification in transaction level modeling of hardware/software systems

Timing analysis and verification are important parts of the system design. Accelerating these activities can drastically speedup the overall design process. In this paper we present a model of timing specification that can be used for acceleration of design space exploration in transaction level modeling (TLM) design flow. To our knowledge, there is no accepted methodology for timing specification representation in TLM till now. We propose to use a combination of two paradigms in the design process: TLM on one hand and a methodology to express timing between different transactions on the other hand.