Ultra-fine-grain field-programmable VLSI using multiple-valued source-coupled logic

An ultra-fine-grain field-programmable VLSI processor, using multiple-valued source-coupled logic, called MV-FPVLSI is proposed for implementing special-purpose processors. To reduce the complexity of the interconnection blocks, a bit-serial pipeline architecture is employed. It also involves a program-counter-less processor architecture, based on direct allocation. The MV-FPVLSI consists of cells which are arranged in a 2D mesh array. Unlike a field programmable gate array (FPGA), data transmission occurs only between two adjacent cells and the overall data transmission delay is very small. Each cell consists of programmable multiple-valued-source coupled logic (MVSCL) circuits. Instead of using lookup tables, ultra-fine-grain logic operations can be carried out using MVSCL circuits. Moreover, using the same hardware resources, each cell can be reconfigured to operate as either a logic function, a memory function or a counter function. Additional versatility can be achieved through current-mode operation.