• DocumentCode
    3266679
  • Title

    Pipelining high-radix SRT division algorithms

  • Author

    Upadhyay, Saurabh ; Stine, James E.

  • Author_Institution
    Oklahoma State Univ., Stillwater
  • fYear
    2007
  • fDate
    5-8 Aug. 2007
  • Firstpage
    309
  • Lastpage
    312
  • Abstract
    This paper shows various ways to pipeline popular SRT division algorithms. Different logic gate families and circuit structures are used to explore possible overheads introduced in each implementation. Simulation results are compared to find out the fastest possible architecture and comparisons are explored from parasitically extracted AMI C5N 0.5 mum layouts.
  • Keywords
    circuit layout; logic gates; pipeline arithmetic; AMI C5N 0.5 mum layouts; circuit structures; high-radix SRT division algorithms; logic gate family; pipeline popular SRT division algorithms; Algorithm design and analysis; Ambient intelligence; CMOS logic circuits; CMOS technology; Computational modeling; Hardware; Latches; Logic circuits; Logic gates; Pipeline processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-1175-7
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2007.4488595
  • Filename
    4488595
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3266679