Design of a configurable fixed-point multiplier for digital signal processor

A configurable fixed-point multiplier for digital signal processing (DSP) applications is proposed in this paper. It is implemented in four pipeline stages. The proposed multiplier supports multiple-precision operations, including one 32×32, two 16×32, two 16×16 or four 8×8 signed/unsigned multiplication operations and 16-bit or 8-bit dot product/double dot product operations. It is modeled in VerilogHDL and synthesized in 0.13 ¿m CMOS technology. The critical path delay of the proposed design is 1.69 ns.