Title :
A 1 GHz decimation filter for Sigma-Delta ADC
Author :
Lian, Yong ; Wei, Ying ; Chandrasekaran, Rajasekaran
Author_Institution :
Nat. Univ. of Singapore, Singapore
Abstract :
This paper presents the implementation of a high-speed decimation filter operating at Giga Hertz that is suitable for high-speed Delta-Sigma analog-to-digital converters. The filter is realized in a non-recursive architecture using a novel full adder and D flip-flop. The filter has been implemented in a 0.18 mum/ 1.8 V CMOS technology for a decimation factor of 4. The operation frequency is 1 GHz and the power consumption of I and Q filters are 6 mW and 4 mW, respectively.
Keywords :
CMOS integrated circuits; analogue-digital conversion; band-pass filters; flip-flops; CMOS technology; decimation filter; flip-flop; frequency 1 GHz; full adder; high-speed delta-sigma analog-to-digital converters; power 4 mW; power 6 mW; sigma-delta ADC; size 0.18 mum; voltage 1.8 V; Band pass filters; CMOS technology; Delta-sigma modulation; Energy consumption; Finite impulse response filter; Frequency; RF signals; Sampling methods; Signal resolution; Superconducting filters;
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2007.4488614
