A 35 ns 64 Mb DRAM using on-chip boosted power supply

Author

Dong-Jae Lee ; Yong-Sik Seok ; Do-Chan Choi ; Jae-Hyeong Lee ; Young-Rae Kim ; Hyeun-Su Kim ; Dong-Soo Jun ; Oh-Hyun Kwon

Author_Institution

Samsung Electron. Co., Kyungki-Do, South Korea

fYear

1992

fDate

4-6 June 1992

Firstpage

64

Lastpage

65

Abstract

An on-chip boosted power supply is necessary for ease of layout and high speed in high density DRAMs. The technique of TTL conversion is a key to designing high speed DRAMs for 3-V operation. The authors present the generation and regulation of an on-chip power supply (V/sub pp/) within 50 mV of the optimum level during operation for a given V/sub cc/. In addition to the regulated V/sub cc/ scheme, improved interface circuit techniques are employed to achieve fast input and output conversion with good noise margins. An experimental 64-Mb DRAM is designed. A typical access time of 35 ns is obtained by measurement.<>

Keywords

BiCMOS integrated circuits; DRAM chips; power supply circuits; 3 V; 3-V operation; 35 ns; 64 Mbit; TTL conversion; ease of layout; fast input conversions; fast output conversions; high density DRAMs; high speed; interface circuit techniques; noise margins; on-chip boosted power supply; Capacitors; Circuit noise; Clamps; Detectors; MOS devices; Power generation; Power supplies; Random access memory; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229238

Filename

229238