DocumentCode
3267093
Title
Low voltage ULSI design: the lower, the better?
Author
Shimohigashi, K. ; Seki, K.
Author_Institution
Hitachi Ltd., Tokyo, Japan
fYear
1992
fDate
4-6 June 1992
Firstpage
54
Lastpage
58
Abstract
An overview of low-voltage ULSI circuit design is presented, beginning with a discussion of the low voltage limit. Logic circuits employing CMOS technology and SRAM and DRAM memory circ.uits are described. Low-voltage analog circuit technology using smart power technology is presented. The switching energies of various electron devices are compared with that of the brain cell in order to gain insight on the minimum energy function.<>
Keywords
CMOS integrated circuits; DRAM chips; SRAM chips; VLSI; integrated circuit technology; CMOS technology; DRAM; SRAM; analog circuit technology; brain cell; electron devices; low voltage limit; low-voltage ULSI circuit design; minimum energy function; smart power technology; switching energies; Analog circuits; CMOS logic circuits; CMOS memory circuits; CMOS technology; Circuit synthesis; Electron devices; Logic circuits; Low voltage; Random access memory; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location
Seattle, WA, USA
Print_ISBN
0-7803-0701-1
Type
conf
DOI
10.1109/VLSIC.1992.229241
Filename
229241
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